1. Field of the Invention
This invention is related to the field of integrated circuits and, more particularly, to synchronous communications among digital circuitry.
2. Description of the Related Art
As integrated circuit fabrication technologies continue to advance, the amount of circuitry that can be integrated onto one chip continues to increase and the operating frequencies for the clocks on the integrated circuits also continue to increase. Various circuitry within the integrated circuit may operate within different clock domains, in some cases. Even if the integrated circuit has a single clock domain, other integrated circuits may have different clock domains and thus communications between integrated circuits may cross clock domains.
High speed, low latency communication often requires that the communication be completed synchronously. If the communication is not synchronous, latency is generally introduced to transfer the data between clock domains (e.g. using first-in, first-out buffers, or FIFOs).
In some cases, within a given integrated circuit, clock tree delays in various physical locations can be matched so that synchronous communication can be accomplished. However, especially in cases in which wide operating voltage ranges are supported and in which different portions of the integrated circuit can operate at different supply voltages, matching the clock trees across all combinations of operating voltages, frequencies, and fabrication process variations is prohibitively difficult.